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SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

12.5

Functional Description

12.5.1

Test Pin

One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied

at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufac-

turing test.

12.5.2

EmbeddedICE

(Embedded In-circuit Emulator)

The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port.The internal state of the ARM7TDMI is exam-

ined through an ICE/JTAG port.

The ARM7TDMI processor contains hardware extensions for advanced debugging features:

In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of

the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system.

In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor

program running on the ARM7TDMI processor.

There are three scan chains inside the ARM7TDMI processor that support testing, debugging, and programming of

the Embedded ICE. The scan chains are controlled by the ICE/JTAG port.

EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG

operations. A chip reset must be performed after JTAGSEL is changed.

For further details on the EmbeddedICE, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B).

12.5.3

Debug Unit

The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace pur-

poses and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover,

the association with two peripheral data controller channels permits packet handling of these tasks with processor

time reduced to a minimum.

The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the

ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to

the system through the ICE interface.

A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal

configuration.

Table 12-2.

SAM7S Series Debug Unit Chip ID

Chip Name

Chip ID

AT91SAM7S16 Rev A

0x27050240

AT91SAM7S161 Rev A

0x27050241

AT91SAM7S32 Rev A

0x27080340

AT91SAM7S32 Rev B

0x27080341

AT91SAM7S321 Rev A

0x27080342

AT91SAM7S64 Rev A

0x27090540

AT91SAM7S64 Rev B

0x27090543

AT91SAM7S64 Rev C

0x27090544

AT91SAM7S128 Rev A

0x270C0740

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